1. Field of the Invention
The disclosure herein pertains to materials and methods for soldering one electrical component to another, for example, in the use of specially prepared solder films to connect chips and other circuit components to printed circuit boards (PCBs) or other substrates.
2. Description of the Related Art
A wafer-level chip scale package (package) is an integrated circuit assembled at the wafer level. The package provides a physical interface between each pad of a chip and a corresponding circuit connection, e.g., a PCB, interposer, or another chip in a chip-on-chip installation. Intra-package connections may extend straight and vertically through the package from the chip to the PCB so that the package has the same width and depth as the chip, thereby reducing or eliminating wasted space. Utilizing a package saves space and weight when compared to face-up chip placement utilizing wire connections between a chip and PCB.
Solder balls may be used to connect the chip to the PCB, for example, using automated ‘flip-chip’ processing equipment as shown in U.S. Pat. No. 5,918,792 issued to Stumpe et al. Generally, each solder ball connects a chip to conductive traces on the PCB. The chip contains a socket that is made of adhesive and conductive materials bonded to the wafer in an area of the chip often referred to as the pad. Each socket retains a selectively placed preformed solder ball as an aid to solder-coupling the chip with the substrate. The pad is a conductive area on the wafer where either conductive material is applied to the chip or ion implantation renders the wafer conductive. Although silicon wafers are most commonly used, other materials such as gallium arsenide are also utilized.
With preformed solder balls positioned on the socket and the chip positioned on the PCB or other circuit connection, the preformed solder balls are heated to at least their melting point. Adhesion forces pull the molten solder over the socket and circuit connection to establish an electrical contact between the chip and the circuit connection. The process of melting the preformed solder ball to form an installed solder ball that couples the socket and the circuit connection is known as “reflow.” The socket resides in electrical contact with conductive traces on the PCB, and these traces operably connect the chip to other PCB components.
Pads include a socket area that may contain a solder receptacle and contact materials. Other portions of the pad may be protected by passivation and polymer layers. As there is difficulty in directly bonding solder to silicon or other wafer materials, the contact materials on the socket are often formed by an under-bump metallization (UBM) layer and an adhesion layer. The adhesion layer, e.g., aluminum, aluminum-copper, connects the pad to the UBM, which is capable of bonding with solder. The solder receptacle may be coextensive with the surface of the UBM, such that the socket boundaries are defined by the surface of the UBM where the perimeter of the socket is formed by voids in passivation and polymer layers. The passivation layer is a dielectric and may protect embedded circuits from contamination or physical damage. The passivation layer may, for example, be formed of polysilicon or oxinitride. The polymer layer provides additional dielectric properties and masks the package for etching, which exposes the UBM and forms the sockets. In some applications, the UBM is applied to the entire void formed in the passivation and polymer layers as a lining in the etched void. In such an application, the socket is defined by the exposed surface of the UBM.
After application of the UBM, the passivation layer may be applied to the pad and etched to form a plurality of openings exposing the UBM layer. A polymer layer, for example a benzocyclobutane (BCB) layer, is next applied to the passivation layer. The BCB layer is also etched to form a plurality of openings, each corresponding to, and aligning with, an opening in the passivation layer. Together, the adhesion layer, UBM layer, and openings in the passivation and BCB layers form a cavity or socket that may be used to contact an installed solder ball.
Prior art packages are typically assembled by placing preformed solder balls at selected socket locations on the chip. The chip is then placed in a predetermined positional alignment such that each preformed solder ball contacts the socket where it resides and conductive traces on the PCB or other circuit connection. The preformed solder balls are reflown to complete the connection between the trace and the UBM layer. Optionally, an underfill resin is applied to the space between solder balls. The resin provides shock-load tolerance beyond the limits of the solder balls alone. The chip may be reinforced by attaching the solder balls to a ceramic carrier, such as an interposer with conductive vias, for example, to enhance rigidity when the PCB is too flexible or as a manufacturing aid to increase solder ball installation alignment tolerances. The interposer is then attached to the PCB.
Packages often have different sockets that connect, for example, with low-current, data (I/O) circuits and high-current, power circuits. Both I/O and power circuits utilize solder ball connections. A single solder ball is often inadequate to carry the load of power circuits. Therefore, the load of a power circuit may be shared across a plurality of electrically parallel solder ball connections. Some installations may require additional solder ball connections to provide adequate heat dissipation from the chip.
Although the prior art solder-ball package provides many benefits, problems remain. Power connections require a greater current capacity compared to I/O connections. As a result, these high-current connections may require multiple solder balls to handle the required current flow. The use of multiple solder balls imposes additional design constraints. For example, the footprint of multiple solder balls must accommodate the plurality of solder balls and the unused space between each solder ball, e.g., the space between each socket. The resulting package is overly large, and the connection footprint contains wasted space. Additionally, the relatively small cross-sectional area of solder balls limits the chip's ability to transfer heat. Heat may accumulate within a chip and degrade performance. Safe operating temperatures are more easily exceeded, and this circumstance may impose associated operational constraints affecting frequency, current, or voltage. If thermal effects are unmitigated, damage to the chip may occur.
Incomplete reflow and stress cracking exacerbate the problems associated with the limited cross-sectional area of solder balls. As chip processing activity fluctuates, associated variable power draw and near-constant electrical resistance produce a corresponding fluctuation in heat, resulting in thermal expansion and contraction of the package and components therein. These fluctuations, known as thermal cycling, create stresses on the connections, for example, because materials of the package do not have the same coefficients of thermal expansion. Thermal stress may lead to fatigue cracks or to complete breakage of contact with a solder ball. Additionally, incomplete reflow further compounds the stress. Incomplete reflow occurs when a preformed solder ball melts to form a solder ball but does not achieve complete coverage of the UBM layer or other connection area. The resulting incomplete connection has a diminished cross-sectional area, which provides a further diminution of performance and an increased probability of cracking and breakage.